AM29LV160

Am29LV160B

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

sSingle power supply operation

—Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications—Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessorssManufactured on 0.32 µm process technologysHigh performance

—Full voltage range: access times as fast as 80 ns—Regulated voltage range: access times as fast as 70 nssUltra low power consumption (typical values at 5MHz)—200 nA Automatic Sleep mode current—200 nA standby mode current—9 mA read current

—20 mA program/erase currentsFlexible sector architecture

—One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one Kbyte sectors (byte mode)

—One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32 Kword sectors (word mode)—Supports full chip erase—Sector Protection features:

A hardware method of locking a sector to prevent any program or erase operations within that sectorSectors can be locked in-system or via programming equipment

Temporary Sector Unprotect feature allows code changes in previously locked sectorssUnlock Bypass Program Command

—Reduces overall programming time when issuing multiple program command sequences

sTop or bottom boot block configurations availablesEmbedded Algorithms

—Embedded Erase algorithm automatically

preprograms and erases the entire chip or any combination of designated sectors—Embedded Program algorithm automatically writes and verifies data at specified addressessMinimum 1,000,000 write cycle guarantee persectors20-year data retention at 125°C

—Reliable operation for the life of the systemsPackage option—48-ball FBGA—48-pin TSOP—44-pin SO

sCFI (Common Flash Interface) compliant—Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devicessCompatibility with JEDEC standards—Pinout and software compatible with single-power supply Flash—Superior inadvertent write protection

sData# Polling and toggle bits

—Provides a software method of detecting program or erase operation completionsReady/Busy# pin (RY/BY#)

—Provides a hardware method of detecting

program or erase cycle completion (not available on 44-pin SO)sErase Suspend/Erase Resume

—Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operationsHardware reset pin (RESET#)

—Hardware method to reset the device to reading array data

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This DataSheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 21358Rev: GAmendment/+1Issue Date: February 1999

GENERAL DESCRIPTION

The Am29LV160B is a 16 Mbit, 3.0 Volt-only Flash memoryorganized as 2,097,152 bytes or 1,048,576 words. Thedevice is offered in 48-ball FBGA, 44-pin SO, and 48-pinTSOP packages. The word-wide data (x16) appears onDQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0.This device is designed to be programmed in-system withthe standard system 3.0 volt VCC supply. A 12.0 V VPP or 5.0VCC are not required for write or erase operations. Thedevice can also be programmed in standardEPROMprogrammers.

The device offers access times of 70, 80, 90, and 120 ns,allowing high speed microprocessors to operatewithout wait states. To eliminate bus contention thedevice has separate chip enable (CE#), write enable(WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power sup-ply for both read and write functions. Internally gener-ated and regulated voltages are provided for theprogram and erase operations.

The Am29LV160B is entirely command set compatiblewith the JEDEC single-power-supply Flash stan-dard. Commands are written to the command registerusing standard microprocessor write timings. Registercontents serve as input to an internal state-machinethat controls the erase and programming circuitry.Write cycles also internally latch addresses and dataneeded for the programming and erase operations.Reading data out of the device is similar to readingfrom other Flash or EPROM devices.

Device programming occurs by executing the programcommand sequence. This initiates the EmbeddedProgram algorithm—an internal algorithm that auto-matically times the program pulse widths and verifiesproper cell margin. The Unlock Bypass mode facili-tates faster programming times by requiring only twowrite cycles to program data instead of four.

Device erasure occurs by executing the erase com-mand sequence. This initiates the Embedded Erasealgorithm—an internal algorithm that automaticallypreprograms the array (if it is not already programmed)before executing the erase operation. During erase, the

device automatically times the erase pulse widths andverifies proper cell margin.

The host system can detect whether a program orerase operation is complete by observing the RY/BY#pin, or by reading the DQ7 (Data# Polling) and DQ6(toggle) status bits. After a program or erase cycle hasbeen completed, the device is ready to read array dataor accept another command.

The sector erase architecture allows memory sectorsto be erased and reprogrammed without affecting thedata contents of other sectors. The device is fullyerased when shipped from the factory.

Hardware data protection measures include a low VCCdetector that automatically inhibits write operations dur-ing power transitions. The hardware sector protectionfeature disables both program and erase operations inany combination of the sectors of memory. This can beachieved in-system or via programming equipment.The Erase Suspend/Erase Resume feature enablesthe user to put erase on hold for any period of time toread data from, or program data to, any sector that isnot selected for erasure. True background erase canthus be achieved.

The hardware RESET# pin terminates any operationin progress and resets the internal state machine toreading array data. The RESET# pin may be tied to thesystem reset circuitry. A system reset would thus alsoreset the device, enabling the system microprocessorto read the boot-up firmware from the Flash memory.The device offers two power-saving features. When ad-dresses have been stable for a specified amount oftime, the device enters the automatic sleep mode.The system can also place the device into the standbymode. Power consumption is greatly reduced in boththese modes.

AMD’s Flash technology combines years of Flashmemory manufacturing experience to produce thehighest levels of quality, reliability and cost effectiveness.The device electrically erases all bits within a sectorsimultaneously via Fowler-Nordheim tunneling. Thedata is programmed using hot electron injection.

2Am29LV160B

PRODUCT SELECTOR GUIDE

Family Part NumberSpeed Option

Regulated Voltage Range: VCC =3.0–3.6 VFull Voltage Range: VCC = 2.7–3.6 V

70703070R

80808030

90909035

12012012050

Am29LV160B

Max access time, ns (tACC)Max CE# access time, ns (tCE)Max OE# access time, ns (tOE)

Note:See “AC Characteristics” for full specifications.BLOCK DIAGRAM

RY/BY#

VCCVSSRESET#

Sector SwitchesErase VoltageGenerator

Input/OutputBuffersDQ0–DQ15 (A-1)

WE#BYTE#

StateControlCommandRegister

PGM VoltageGenerator

Chip EnableOutput Enable

Logic

STB

DataLatch

CE#OE#

STB

VCC Detector

Timer

Address LatchY-DecoderY-Gating

X-Decoder

Cell Matrix

A0–A19

21358G-1

Am29LV160B3

CONNECTION DIAGRAMS

A15A14A13A12A11A10A9A8A19NCWE#RESET#NCNCRY/BY#A18A17A7A6A5A4A3A2A11234567101112131415161718192021222324Standard TSOP4847454443424140393837363534333231302928272625A16BYTE#VSSDQ15/A-1DQ7DQ14DQ6DQ13DQ5DQ12DQ4VCCDQ11DQ3DQ10DQ2DQ9DQ1DQ8DQ0OE#VSSCE#A0A16BYTE#VSSDQ15/A-1DQ7DQ14DQ6DQ13DQ5DQ12DQ4VCCDQ11DQ3DQ10DQ2DQ9DQ1DQ8DQ0OE#VSSCE#A01234567101112131415161718192021222324Reverse TSOP4847454443424140393837363534333231302928272625A15A14A13A12A11A10A9A8A19NCWE#RESET#NCNCRY/BY#A18A17A7A6A5A4A3A2A121358G-2

4Am29LV160B

CONNECTION DIAGRAMS

RESET#A18A17A7A6A5A4A3A2A1A0CE#VSSOE#DQ0DQ8DQ1DQ9DQ2DQ10DQ3DQ1112345671011121314151617181920212244434241403938373635343332313029282726252423WE#A19A8A9A10A11A12A13A14A15A16BYTE#VSSDQ15/A-1DQ7DQ14DQ6DQ13DQ5DQ12DQ4VCCSOFBGATop View, Balls Facing DownA6A13A5A9A4WE#A3RY/BY#A2A7A1A3B6A12B5A8B4RESET#B3NCB2A17B1A4C6A14C5A10C4NCC3A18C2A6C1A2D6A15D5A11D4A19D3NCD2A5D1A1E6A16E5DQ7E4DQ5E3DQ2E2DQ0E1A0F6G6H6VSSH5DQ6H4DQ4H3DQ3H2DQ1H1VSSBYTE#DQ15/A-1F5DQ14F4DQ12F3DQ10F2DQ8F1CE#G5DQ13G4VCCG3DQ11G2DQ9G1OE#21358G-3

Special Handling Instructions

Special handling is required for Flash Memory productsin FBGA packages.

Flash memory devices in FBGA packages may bedamaged if exposed to ultrasonic cleaning methods.The package and/or data integrity may be compromisedif the package body is exposed to temperatures above150°C for prolonged periods of time.

Am29LV160B5

PIN CONFIGURATION

A0–A19

=20 addresses

DQ0–DQ14=15 data inputs/outputs

DQ15/A-1=DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)BYTE#CE#OE#WE#RESET#RY/BY#VCC

=Selects 8-bit or 16-bit mode=Chip enable= Output enable=Write enable=Hardware reset pin= Ready/Busy output

(N/A SO 044)

=3.0 volt-only single power supply

(see Product Selector Guide for speedoptions and voltage supply tolerances)=Device ground

=Pin not connected internally

LOGIC SYMBOL

20

A0–A19

DQ0–DQ15

(A-1)

CE#OE#WE#RESET#BYTE#

RY/BY#

(N/A SO 044)

16 or 8

21358G-4

VSSNC

6Am29LV160B

ORDERING INFORMATIONStandard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-nation) is formed by a combination of the elements below.

AM29LV160BT70REC

OPTIONAL PROCESSINGBlank=Standard Processing B=Burn-in

(Contact an AMD representative for more information)TEMPERATURE RANGE

C=Commercial (0°C to +70°C)I=Industrial (–40°C to +85°C)E=Extended (–55°C to +125°C)

PACKAGE TYPE

E=48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

F=48-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR048)

S=44-Pin Small Outline Package (SO 044)WC=48-ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 8 x 9 mm package (FBC048)SPEED OPTION

See Product Selector Guide and Valid CombinationsBOOT CODE SECTOR ARCHITECTURET=Top SectorB=Bottom Sector

DEVICE NUMBER/DESCRIPTIONAm29LV160B

16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS Flash Memory3.0 Volt-only Read, Program, and Erase

office to confirm availability of specific valid combinations andto check on newly released combinations.

Valid Combinations For TSOP and SO PackagesAM29LV160BT70R,AM29LV160BB70RAM29LV160BT80,AM29LV160BB80AM29LV160BT90,AM29LV160BB90AM29LV160BT120,AM29LV160BB120

Valid Combinations

Valid Combinations list configurations planned to be sup-ported in volume for this device. Consult the local AMD sales

EC, EI, EE, FC, FI, FE,SC, SI, SEEC, FC, SC

Valid Combinations for FBGA PackagesOrder Number

AM29LV160BT70R,AM29LV160BB70RAM29LV160BT80,AM29LV160BB80AM29LV160BT90,AM29LV160BB90AM29LV160BT120,AM29LV160BB120

WCC

Package MarkingL160BT70R,L160BB70RL160BT80V,L160BB80V

WCC,

L160BT90V,

WCI,

L160BB90V

WCE

L160BT12V,L160BB12V

C, I, EC

Am29LV160B7

DEVICE BUS OPERATIONS

This section describes the requirements and use of thedevice bus operations, which are initiated through theinternal command register. The command register it-self does not occupy any addressable memory loca-tion. The register is composed of latches that store thecommands, along with the address and data informa-tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-chine. The state machine outputs dictate the function ofthe device. Table 1 lists the device bus operations, theinputs and control levels they require, and the resultingoutput. The following subsections describe each ofthese operations in further detail.

Table 1.Am29LV160B Device Bus Operations

DQ8–DQ15

Addresses(Note 1)

AINAINXXX

Sector Address, A6 = L, A1 = H,

A0 = LSector Address, A6 = H, A1 = H,

A0 = L

AIN

DQ0–DQ7DOUTDINHigh-ZHigh-ZHigh-ZDIN

BYTE#= VIHDOUTDINHigh-ZHigh-ZHigh-ZX

BYTE# = VIL

DQ8–DQ14 = High-Z,

DQ15 = A-1

High-ZHigh-ZHigh-ZX

Operation

ReadWriteStandbyOutput DisableReset

Sector Protect (Note 2)

CE#LLVCC ± 0.3 VLXL

OE#WE#RESET#LHXHXH

HLXHXL

HHVCC ± 0.3 VHLVID

Sector Unprotect (Note 2)Temporary Sector Unprotect

LX

HX

LX

VIDVID

DINDIN

XDIN

XHigh-Z

Legend:L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data OutNotes:1.Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).2.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Protection/Unprotection” section.Word/Byte Configuration

The BYTE# pin controls whether the device data I/Opins DQ15–DQ0 operate in the byte or word configura-tion. If the BYTE# pin is set at logic ‘1’, the device is inword configuration, DQ15–DQ0 are active and con-trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byteconfiguration, and only data I/O pins DQ0–DQ7 are ac-tive and controlled by CE# and OE#. The data I/O pinsDQ8–DQ14 are tri-stated, and the DQ15 pin is used asan input for the LSB (A-1) address function.

main at VIH. The BYTE# pin determines whether the de-vice outputs array data in words or bytes.

The internal state machine is set for reading arraydata upon device power-up, or after a hardware reset.This ensures that no spurious alteration of the mem-ory content occurs during the power transition. Nocommand is necessary in this mode to obtain arraydata. Standard microprocessor read cycles that as-sert valid addresses on the device address inputs pro-duce valid data on the device data outputs. The deviceremains enabled for read access until the commandregister contents are altered.

See “Reading Array Data” for more information. Referto the AC Read Operations table for timing specifica-tions and to Figure 13 for the timing diagram. ICC1 inthe DC Characteristics table represents the active cur-rent specification for reading array data.

Requirements for Reading Array Data

To read array data from the outputs, the system mustdrive the CE# and OE# pins to VIL. CE# is the powercontrol and selects the device. OE# is the output controland gates array data to the output pins. WE# should re-

8Am29LV160B

Writing Commands/Command Sequences

To write a command or command sequence (whichincludes programming data to the device and erasingsectors of memory), the system must drive WE# andCE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determineswhether the device accepts program data in bytes orwords. Refer to “Word/Byte Configuration” for moreinformation.

The device features an Unlock Bypass mode to facili-tate faster programming. Once the device enters theUnlock Bypass mode, only two write cycles arerequired to program a word or byte, instead of four. The“Word/Byte Program Command Sequence” sectionhas details on programming data to the device usingboth standard and Unlock Bypass commandsequences.

An erase operation can erase one sector, multiple sec-tors, or the entire device. Tables 2 and 3 indicate theaddress space that each sector occupies. A “sectoraddress” consists of the address bits required touniquely select a sector. The “Command Definitions”section has details on erasing a sector or the entirechip, or suspending/resuming the erase operation.After the system writes the autoselect commandsequence, the device enters the autoselect mode. Thesystem can then read autoselect codes from theinternal register (which is separate from the memoryarray) on DQ7–DQ0. Standard read cycle timings applyin this mode. Refer to the “Autoselect Mode” and“Autoselect Command Sequence” sections for moreinformation.

ICC2 in the DC Characteristics table represents the ac-tive current specification for the write mode. The “ACCharacteristics” section contains timing specificationtables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system maycheck the status of the operation by reading the statusbits on DQ7–DQ0. Standard read cycle timings and ICCread specifications apply. Refer to “Write OperationStatus” for more information, and to “AC Characteris-tics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device,it can place the device in the standby mode. In thismode, current consumption is greatly reduced, and theoutputs are placed in the high impedance state, inde-pendent of the OE# input.

The device enters the CMOS standby mode when theCE# and RESET# pins are both held at VCC ± 0.3 V.(Note that this is a more restricted voltage range thanVIH.) If CE# and RESET# are held at VIH, but not withinVCC ± 0.3 V, the device will be in the standby mode, butthe standby current will be greater. The device requiresstandard access time (tCE) for read access when thedevice is in either of these standby modes, before it isready to read data.

If the device is deselected during erasure or program-ming, the device draws active current until theoperation is completed.

In the DC Characteristics table, ICC3 and ICC4 repre-sents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash deviceenergy consumption. The device automatically enablesthis mode when addresses remain stable for tACC + 30ns. The automatic sleep mode is independent of theCE#, WE#, and OE# control signals. Standard addressaccess timings provide new data when addresses arechanged. While in sleep mode, output data is latchedand always available to the system. ICC4 in the DCCharacteristics table represents the automatic sleepmode current specification.

Am29LV160B9

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset-ting the device to reading array data. When the systemdrives the RESET# pin to VIL for at least a period of tRP,the device immediately terminates any operation inprogress, tristates all data output pins, and ignores allread/write attempts for the duration of the RESET#pulse. The device also resets the internal state ma-chine to reading array data. The operation that was in-terrupted should be reinitiated once the device is readyto accept another command sequence, to ensure dataintegrity.

Current is reduced for the duration of the RESET#pulse. When RESET# is held at VSS±0.3 V, the devicedraws CMOS standby current (ICC4). If RESET# is heldat VIL but not within VSS±0.3 V, the standby current willbe greater.

The RESET# pin may be tied to the system reset cir-cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-ware from the Flash memory.

If RESET# is asserted during a program or erase op-eration, the RY/BY# pin remains a “0” (busy) until theinternal reset operation is complete, which requires atime of tREADY (during Embedded Algorithms). Thesystem can thus monitor RY/BY# to determinewhether the reset operation is complete. If RESET# isasserted when a program or erase operation is not ex-ecuting (RY/BY# pin is “1”), the reset operation iscompleted within a time of tREADY (not during Embed-ded Algorithms). The system can read data tRH afterthe RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# pa-rameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device isdisabled. The output pins are placed in the high imped-ance state.

10Am29LV160B

Table 2.Sector Address Tables (Am29LV160BT)

Sector Size(Kbytes/Kwords)/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/3232/168/48/416/8

Address Range (in hexadecimal)Byte Mode (x8)000000–00FFFF010000–01FFFF020000–02FFFF030000–03FFFF040000–04FFFF050000–05FFFF060000–06FFFF070000–07FFFF080000–08FFFF090000–09FFFF0A0000–0AFFFF0B0000–0BFFFF0C0000–0CFFFF0D0000–0DFFFF0E0000–0EFFFF0F0000–0FFFFF100000–10FFFF110000–11FFFF120000–12FFFF130000–13FFFF140000–14FFFF150000–15FFFF160000–16FFFF170000–17FFFF180000–18FFFF190000–19FFFF1A0000–1AFFFF1B0000–1BFFFF1C0000–1CFFFF1D0000–1DFFFF1E0000–1EFFFF1F0000–1F7FFF1F8000–1F9FFF1FA000–1FBFFF1FC000–1FFFFF

Word Mode (x16)00000–07FFF08000–0FFFF10000–17FFF18000–1FFFF20000–27FFF28000–2FFFF30000–37FFF38000–3FFFF40000–47FFF48000–4FFFF50000–57FFF58000–5FFFF60000–67FFF68000–6FFFF70000–77FFF78000–7FFFF80000–87FFF88000–8FFFF90000–97FFF98000–9FFFFA0000–A7FFFA8000–AFFFFB0000–B7FFFB8000–BFFFFC0000–C7FFFC8000–CFFFFD0000–D7FFFD8000–DFFFFE0000–E7FFFE8000–EFFFFF0000–F7FFFF8000–FBFFFFC000–FCFFFFD000–FDFFFFE000–FFFFF

SectorSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10SA11SA12SA13SA14SA15SA16SA17SA18SA19SA20SA21SA22SA23SA24SA25SA26SA27SA28SA29SA30SA31SA32SA33SA34

A1900000000000000001111111111111111111

A1800000000111111110000000011111111111

A1700001111000011110000111100001111111

A1600110011001100110011001100110011111

A1501010101010101010101010101010101111

A14XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0111

A13XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX001

A12XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01X

Note:Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section.Am29LV160B11

Table 3.

Sector Address Tables (Am29LV160BB)

Sector Size(Kbytes/Kwords)

16/88/48/432/16/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32

Address Range (in hexadecimal)Byte Mode (x8)000000–003FFF004000–005FFF006000–007FFF008000–00FFFF010000–01FFFF020000–02FFFF030000–03FFFF040000–04FFFF050000–05FFFF060000–06FFFF070000–07FFFF080000–08FFFF090000–09FFFF0A0000–0AFFFF0B0000–0BFFFF0C0000–0CFFFF0D0000–0DFFFF0E0000–0EFFFF0F0000–0FFFFF100000–10FFFF110000–11FFFF120000–12FFFF130000–13FFFF140000–14FFFF150000–15FFFF160000–16FFFF170000–17FFFF180000–18FFFF190000–19FFFF1A0000–1AFFFF1B0000–1BFFFF1C0000–1CFFFF1D0000–1DFFFF1E0000–1EFFFF1F0000–1FFFFF

Word Mode (x16)00000–01FFF02000–02FFF03000–03FFF04000–07FFF08000–0FFFF10000–17FFF18000–1FFFF20000–27FFF28000–2FFFF30000–37FFF38000–3FFFF40000–47FFF48000–4FFFF50000–57FFF58000–5FFFF60000–67FFF68000–6FFFF70000–77FFF78000–7FFFF80000–87FFF88000–8FFFF90000–97FFF98000–9FFFFA0000–A7FFFA8000–AFFFFB0000–B7FFFB8000–BFFFFC0000–C7FFFC8000–CFFFFD0000–D7FFFD8000–DFFFFE0000–E7FFFE8000–EFFFFF0000–F7FFFF8000–FFFFF

SectorSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10SA11SA12SA13SA14SA15SA16SA17SA18SA19SA20SA21SA22SA23SA24SA25SA26SA27SA28SA29SA30SA31SA32SA33SA34

A1900000000000000000001111111111111111

A1800000000000111111110000000011111111

A1700000001111000011110000111100001111

A1600000110011001100110011001100110011

A1500001010101010101010101010101010101

A140001XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

A13011XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

A12X01XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Note:Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the “Word/Byte Configuration” section.12Am29LV160B

Autoselect Mode

The autoselect mode provides manufacturer and de-vice identification, and sector protection verification,through identifier codes output on DQ7–DQ0. Thismode is primarily intended for programming equipmentto automatically match a device to be programmed withits corresponding programming algorithm. However,the autoselect codes can also be accessed in-systemthrough the command register.

When using programming equipment, the autoselectmode requires VID (11.5 V to 12.5 V) on address pinA9. Address pins A6, A1, and A0 must be as shown in

Table 4. In addition, when verifying sector protection,the sector address must appear on the appropriatehighest order address bits (see Tables 2 and 3). Table4 shows the remaining address bits that are don’t care.When all necessary bits have been set as required, theprogramming equipment may then read the corre-sponding identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the hostsystem can issue the autoselect command via thecommand register, as shown in Table 9. This methoddoes not require VID. See “Command Definitions” fordetails on using the autoselect mode.

Table 4.Am29LV160B Autoselect Codes (High Voltage Method)

A19A11

toto

WE#A12A10HHHHH

X

X

VID

X

L

X

L

H

X

X

VID

X

L

X

L

H

X

X

A8toA7X

A5toA2X

DQ8toDQ15X22hX22hXX

Sector Protection Verification

L

L

H

SA

X

VID

X

L

X

H

L

X

DQ7toDQ001hC4hC4h49h49h01h (protected)00h (unprotected)

DescriptionManufacturer ID: AMDDevice ID: Am29LV160B(Top Boot Block)Device ID: Am29LV160B

(Bottom Boot Block)

ModeCE#L

OE#LLLLL

A9VID

A6L

A1L

A0L

WordByteWordByte

LLLL

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.Note: The autoselect codes may also be accessed in-system via command sequences. See Table 9.Sector Protection/Unprotection

The hardware sector protection feature disables bothprogram and erase operations in any sector. The hard-ware sector unprotection feature re-enables both pro-gram and erase operations in previously protectedsectors.

The device is shipped with all sectors unprotected.AMD offers the option of programming and protectingsectors at its factory prior to shipping the devicethrough AMD’s ExpressFlash™ Service. Contact anAMD representative for details.

It is possible to determine whether a sector is protectedor unprotected. See “Autoselect Mode” for details.Sector protection/unprotection can be implemented viatwo methods.

The primary method requires VID on the RESET# pinonly, and can be implemented either in-system or viaprogramming equipment. Figure 2 shows the algo-rithms and Figure 23 shows the timing diagram. Thismethod uses standard microprocessor bus cycle tim-ing. For sector unprotect, all unprotected sectors mustfirst be protected prior to the first sector unprotect writecycle.

The alternate method intended only for programmingequipment requires VID on address pin A9 and OE#.This method is compatible with programmer routineswritten for earlier 3.0 volt-only AMD flash devices. De-tails on this method are provided in a supplement, pub-lication number 21468. Contact an AMD representativeto request a copy.

Am29LV160B13

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-ously protected sectors to change data in-system. TheSector Unprotect mode is activated by setting the RE-SET# pin to VID. During this mode, formerly protectedsectors can be programmed or erased by selecting thesector addresses. Once VID is removed from the RE-SET# pin, all the previously protected sectors areprotectedagain. Figure shows the algorithm, and Fig-ure 22 shows the timing diagrams, for this feature.

START

RESET# = VID

(Note 1)Perform Erase orProgram Operations

RESET# = VIH

Temporary SectorUnprotect Completed

(Note 2)

21358G-5

Notes:1.All protected sectors unprotected.2.All previously protected sectors are protected onceagain.Figure 1.Temporary Sector Unprotect Operation

14Am29LV160B

STARTPLSCNT = 1RESET# = VIDWait 1 µsProtect all sectors:The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect addressSTARTPLSCNT = 1RESET# = VIDWait 1 µsTemporary SectorUnprotect ModeNoFirst Write Cycle = 60h?YesSet up sectoraddressSector Protect:Write 60h to sectoraddress withA6 = 0, A1 = 1, A0 = 0Wait 150 µsVerify Sector Protect: Write 40h to sector addresswith A6 = 0, A1 = 1, A0 = 0Read from sector addresswith A6 = 0, A1 = 1, A0 = 0NoNoFirst Write Cycle = 60h?YesAll sectorsprotected?YesSet up first sectoraddressSector Unprotect:Write 60h to sectoraddress withA6 = 1, A1 = 1, A0 = 0Temporary SectorUnprotect ModeIncrementPLSCNTResetPLSCNT = 1Wait 15 msVerify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0Read from sector addresswith A6 = 1, A1 = 1, A0 = 0Set upnext sectoraddressNoNoPLSCNT= 25?YesData = 01h?YesYesDevice failedProtect anothersector?NoRemove VID from RESET#Write reset commandIncrementPLSCNTNoNoPLSCNT= 1000?YesData = 00h?YesDevice failedLast sectorverified?YesNoSector ProtectAlgorithmSector ProtectcompleteSector UnprotectAlgorithmRemove VID from RESET#Write reset commandSector Unprotectcomplete21358G-6

Figure 2.In-System Sector Protect/Unprotect Algorithms

Am29LV160B15

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification out-lines device and host system software interrogationhandshake, which allows specific vendor-specifiedsoftware algorithms to be used for entire families ofdevices. Software support can then be device-indepen-dent, JEDEC ID-independent, and forward- and back-ward-compatible for the specified flash device families.Flash vendors can standardize their existing interfacesfor long-term compatibility.

This device enters the CFI Query mode when thesystem writes the CFI Query command, 98h, toaddress 55h in word mode (or address AAh in bytemode), any time the device is ready to read array data.

The system can read CFI information at the addressesgiven in Tables 5–8. In word mode, the upper addressbits (A7–MSB) must be all zeros. To terminate readingCFI data, the system must write the reset command. The system can also write the CFI query commandwhen the device is in the autoselect mode. The deviceenters the CFI query mode, and the system can readCFI data at the addresses given in Tables 5–8. Thesystem must write the reset command to return thedevice to the autoselect mode.

For further information, please refer to the CFI Specifi-cation and CFI Publication 100, available via the WorldWide Web at http://www.amd.com/products/nvd/over-view/cfi.html. Alternatively, contact an AMD represen-tative for copies of these documents.

Table 5.CFI Query Identification String

Addresses(Word Mode)

10h11h12h13h14h15h16h17h18h19h1Ah

Addresses(Byte Mode)

20h22h24h26h28h2Ah2Ch2Eh30h32h34h

Data0051h0052h0059h0002h0000h0040h0000h0000h0000h0000h0000h

Description

Query Unique ASCII string “QRY”

Primary OEM Command SetAddress for Primary Extended Table

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

16Am29LV160B

Table 6.

Addresses(Word Mode)

1Bh1Ch1Dh1Eh1Fh20h21h22h23h24h25h26h

Addresses(Byte Mode)

36h38h3Ah3Ch3Eh40h42h44h46h48h4Ah4Ch

Data0027h0036h0000h0000h0004h0000h000Ah0000h0005h0000h0004h0000h

System Interface String

Description

VCC Min. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt VCC Max. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

VPP Min. voltage (00h = no VPP pin present)VPP Max. voltage (00h = no VPP pin present)Typical timeout per single byte/word write 2N µs

Typical timeout for Min. size buffer write 2N µs (00h = not supported)Typical timeout per individual block erase 2N ms

Typical timeout for full chip erase 2N ms (00h = not supported)Max. timeout for byte/word write 2N times typicalMax. timeout for buffer write 2N times typical

Max. timeout per individual block erase 2N times typical

Max. timeout for full chip erase 2N times typical (00h = not supported)

Table 7.

Addresses(Word Mode)

27h28h29h2Ah2Bh2Ch2Dh2Eh2Fh30h31h32h33h34h35h36h37h38h39h3Ah3Bh3Ch

Addresses(Byte Mode)

4Eh50h52h54h56h58h5Ah5Ch5Eh60h62hh66h68h6Ah6Ch6Eh70h72h74h76h78h

Data0015h0002h0000h0000h0000h0004h0000h0000h0040h0000h0001h0000h0020h0000h0000h0000h0080h0000h001Eh0000h0000h0001h

Device Geometry Definition

Description

Device Size = 2N byte

Flash Device Interface description (refer to CFI publication 100)Max. number of byte in multi-byte write = 2N (00h = not supported)

Number of Erase Block Regions within deviceErase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

Am29LV160B17

Table 8.

Addresses(Word Mode)

40h41h42h43h44h45h46h47h48h

Addresses(Byte Mode)

80h82h84h86h88h8Ah8Ch8Eh90h

Primary Vendor-Specific Extended Query

Data0050h0052h0049h0031h0030h0000h0002h0001h0001h

Description

Query-unique ASCII string “PRI”Major version number, ASCIIMinor version number, ASCIIAddress Sensitive Unlock

0 = Required, 1 = Not Required

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & WriteSector Protect

0 = Not Supported, X = Number of sectors in per groupSector Temporary Unprotect

00 = Not Supported, 01 = SupportedSector Protect/Unprotect scheme

01 = 29F040 mode, 02 = 29F016 mode,03 = 29F400 mode, 04 = 29LV800A modeSimultaneous Operation

00 = Not Supported, 01 = SupportedBurst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

49h92h0004h

4Ah4Bh4Ch

94h96h98h

0000h0000h0000h

Hardware Data Protection

The command sequence requirement of unlock cyclesfor programming or erasing provides data protectionagainst inadvertent writes (refer to Table 9 for com-mand definitions). In addition, the following hardwaredata protection measures prevent accidental erasureor programming, which might otherwise be caused byspurious system level signals during VCC power-up andpower-down transitions, or from system noise.Low VCC Write Inhibit

When VCC is less than VLKO, the device does not ac-cept any write cycles. This protects data during VCCpower-up and power-down. The command register andall internal program/erase circuits are disabled, and thedevice resets. Subsequent writes are ignored until VCCis greater than VLKO. The system must provide the

proper signals to the control pins to prevent uninten-tional writes when VCC is greater than VLKO.Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# orWE# do not initiate a write cycle.Logical Inhibit

Write cycles are inhibited by holding any one of OE# =VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,CE# and WE# must be a logical zero while OE# is alogical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, thedevice does not accept commands on the rising edgeof WE#. The internal state machine is automaticallyreset to reading array data on power-up.

18Am29LV160B

COMMAND DEFINITIONS

Writing specific address and data commands orsequences into the command register initiates deviceoperations. Table 9 defines the valid register commandsequences. Writing incorrect address and datavalues or writing them in the improper sequenceresets the device to reading array data.

All addresses are latched on the falling edge of WE# orCE#, whichever happens later. All data is latched onthe rising edge of WE# or CE#, whichever happensfirst. Refer to the appropriate timing diagrams in the“AC Characteristics” section.

The reset command may be written between the se-quence cycles in an autoselect command sequence.Once in the autoselect mode, the reset command mustbe written to return to reading array data (also appliesto autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,writing the reset command returns the device to read-ing array data (also applies during Erase Suspend).See “AC Characteristics” for parameters, and to Figure14 for the timing diagram.

Reading Array Data

The device is automatically set to reading array dataafter device power-up. No commands are required toretrieve data. The device is also ready to read arraydata after completing an Embedded Program or Em-bedded Erase algorithm.

After the device accepts an Erase Suspend com-mand, the device enters the Erase Suspend mode.The system can read array data using the standardread timings, except that if it reads at an addresswithin erase-suspended sectors, the device outputsstatus data. After completing a programming opera-tion in the Erase Suspend mode, the system mayonce again read array data with the same exception.See “Erase Suspend/Erase Resume Commands” formore information on this mode.

The system must issue the reset command to re-en-able the device for reading array data if DQ5 goes high,or while in the autoselect mode. See the “Reset Com-mand” section, next.

See also “Requirements for Reading Array Data” in the“Device Bus Operations” section for more information.The Read Operations table provides the read parame-ters, and Figure 13 shows the timing diagram.

Autoselect Command Sequence

The autoselect command sequence allows the hostsystem to access the manufacturer and devices codes,and determine whether or not a sector is protected.Table 9 shows the address and data requirements. Thismethod is an alternative to that shown in Table 4, whichis intended for PROM programmers and requires VIDon address bit A9.

The autoselect command sequence is initiated by writ-ing two unlock cycles, followed by the autoselect com-mand. The device then enters the autoselect mode,and the system may read at any address any numberof times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufac-turer code. A read cycle at address XX01h returns thedevice code. A read cycle containing a sector address(SA) and the address 02h in word mode (or 04h in bytemode) returns 01h if that sector is protected, or 00h if itis unprotected. Refer to Tables 2 and 3 for valid sectoraddresses.

The system must write the reset command to exit theautoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte,depending on the state of the BYTE# pin. Program-ming is a four-bus-cycle operation. The program com-mand sequence is initiated by writing two unlock writecycles, followed by the program set-up command. Theprogram address and data are written next, which inturn initiate the Embedded Program algorithm. Thesystem is not required to provide further controls ortimings. The device automatically generates the pro-gram pulses and verifies the programmed cell margin.Table 9 shows the address and data requirements forthe byte program command sequence.

When the Embedded Program algorithm is complete,the device then returns to reading array data and ad-dresses are no longer latched. The system can deter-mine the status of the program operation by using DQ7,DQ6, or RY/BY#. See “Write Operation Status” for in-formation on these status bits.

Reset Command

Writing the reset command to the device resets the de-vice to reading array data. Address bits are don’t carefor this command.

The reset command may be written between the se-quence cycles in an erase command sequence beforeerasing begins. This resets the device to reading arraydata. Once erasure begins, however, the device ig-nores reset commands until the operation is complete.The reset command may be written between the se-quence cycles in a program command sequence be-fore programming begins. This resets the device toreading array data (also applies to programming inErase Suspend mode). Once programming begins,however, the device ignores reset commands until theoperation is complete.

Am29LV160B19

Any commands written to the device during the Em-bedded Program Algorithm are ignored. Note that ahardware reset immediately terminates the program-ming operation. The Byte Program command se-quence should be reinitiated once the device has resetto reading array data, to ensure data integrity.Programming is allowed in any sequence and acrosssector boundaries. A bit cannot be programmedfrom a “0” back to a “1”. Attempting to do so may haltthe operation and set DQ5 to “1,” or cause the Data#Polling algorithm to indicate the operation was suc-cessful. However, a succeeding read will show that thedata is still “0”. Only erase operations can convert a “0”to a “1”.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-gram bytes or words to the device faster than using thestandard program command sequence. The unlock by-pass command sequence is initiated by first writing twounlock cycles. This is followed by a third write cyclecontaining the unlock bypass command, 20h. The de-vice then enters the unlock bypass mode. A two-cycleunlock bypass program command sequence is all thatis required to program in this mode. The first cycle inthis sequence contains the unlock bypass programcommand, A0h; the second cycle contains the programaddress and data. Additional data is programmed inthe same manner. This mode dispenses with the initialtwo unlock cycles required in the standard programcommand sequence, resulting in faster total program-ming time. Table 9 shows the requirements for the com-mand sequence.

During the unlock bypass mode, only the Unlock By-pass Program and Unlock Bypass Reset commandsare valid. To exit the unlock bypass mode, the systemmust issue the two-cycle unlock bypass reset com-mand sequence. The first cycle must contain the data90h; the second cycle the data 00h. Addresses aredon’t care for both cycles. The device then returns toreading array data.

Figure 3 illustrates the algorithm for the program oper-ation. See the Erase/Program Operations table in “ACCharacteristics” for parameters, and to Figure 17 fortiming diagrams.

STARTWrite ProgramCommand SequenceEmbeddedProgramalgorithm in progressData Poll from SystemVerify Data?NoYesNoIncrement AddressLast Address?YesProgramming Completed21358G-7

Note: See Table 9 for program command sequence.Figure 3.Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erasecommand sequence is initiated by writing two unlockcycles, followed by a set-up command. Two additionalunlock write cycles are then followed by the chip erasecommand, which in turn invokes the Embedded Erasealgorithm. The device does not require the system topreprogram prior to erase. The Embedded Erase algo-rithm automatically preprograms and verifies the entirememory for an all zero data pattern prior to electricalerase. The system is not required to provide any con-trols or timings during these operations. Table 9 showsthe address and data requirements for the chip erasecommand sequence.

Any commands written to the chip during the Embed-ded Erase algorithm are ignored. Note that a hardwarereset during the chip erase operation immediately ter-minates the operation. The Chip Erase command se-quence should be reinitiated once the device hasreturned to reading array data, to ensure data integrity.

20Am29LV160B

The system can determine the status of the erase op-eration by using DQ7, DQ6, DQ2, or RY/BY#. See“Write Operation Status” for information on these sta-tus bits. When the Embedded Erase algorithm is com-plete, the device returns to reading array data andaddresses are no longer latched.

Figure 4 illustrates the algorithm for the erase opera-tion. See the Erase/Program Operations tables in “ACCharacteristics” for parameters, and to Figure 18 fortiming diagrams.

When the Embedded Erase algorithm is complete, thedevice returns to reading array data and addresses areno longer latched. The system can determine the sta-tus of the erase operation by using DQ7, DQ6, DQ2, orRY/BY#. (Refer to “Write Operation Status” for informa-tion on these status bits.)

Figure 4 illustrates the algorithm for the erase opera-tion. Refer to the Erase/Program Operations tables inthe “AC Characteristics” section for parameters, and toFigure 18 for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sectorerase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. Two addi-tional unlock write cycles are then followed by theaddress of the sector to be erased, and the sectorerase command. Table 9 shows the address and datarequirements for the sector erase command sequence.The device does not require the system to preprogramthe memory prior to erase. The Embedded Erase algo-rithm automatically programs and verifies the sector foran all zero data pattern prior to electrical erase. Thesystem is not required to provide any controls or tim-ings during these operations.

After the command sequence is written, a sector erasetime-out of 50 µs begins. During the time-out period,additional sector addresses and sector erase com-mands may be written. Loading the sector erase buffermay be done in any sequence, and the number of sec-tors may be from one sector to all sectors. The time be-tween these additional cycles must be less than 50 µs,otherwise the last address and command might not beaccepted, and erasure may begin. It is recommendedthat processor interrupts be disabled during this time toensure all commands are accepted. The interrupts canbe re-enabled after the last Sector Erase command iswritten. If the time between additional sector erasecommands can be assumed to be less than 50 µs, thesystem need not monitor DQ3. Any command otherthan Sector Erase or Erase Suspend during thetime-out period resets the device to reading arraydata. The system must rewrite the command sequenceand any additional sector addresses and commands.The system can monitor DQ3 to determine if the sectorerase timer has timed out. (See the “DQ3: Sector EraseTimer” section.) The time-out begins from the risingedge of the final WE# pulse in the command sequence.Once the sector erase operation has begun, only theErase Suspend command is valid. All other commandsare ignored. Note that a hardware reset during thesector erase operation immediately terminates the op-eration. The Sector Erase command sequence shouldbe reinitiated once the device has returned to readingarray data, to ensure data integrity.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to in-terrupt a sector erase operation and then read datafrom, or program data to, any sector not selected forerasure. This command is valid only during the sectorerase operation, including the 50 µs time-out periodduring the sector erase command sequence. TheErase Suspend command is ignored if written duringthe chip erase operation or Embedded Program algo-rithm. Writing the Erase Suspend command during theSector Erase time-out immediately terminates thetime-out period and suspends the erase operation. Ad-dresses are “don’t-cares” when writing the Erase Sus-pend command.

When the Erase Suspend command is written during asector erase operation, the device requires a maximumof 20 µs to suspend the erase operation. However,when the Erase Suspend command is written duringthe sector erase time-out, the device immediately ter-minates the time-out period and suspends the eraseoperation.

After the erase operation has been suspended, thesystem can read array data from or program data toany sector not selected for erasure. (The device “erasesuspends” all sectors selected for erasure.) Normalread and write timings and command definitions apply.Reading at any address within erase-suspended sec-tors produces status data on DQ7–DQ0. The systemcan use DQ7, or DQ6 and DQ2 together, to determineif a sector is actively erasing or is erase-suspended.See “Write Operation Status” for information on thesestatus bits.

After an erase-suspended program operation is com-plete, the system can once again read array data withinnon-suspended sectors. The system can determinethe status of the program operation using the DQ7 orDQ6 status bits, just as in the standard program oper-ation. See “Write Operation Status” for more informa-tion.

The system may also write the autoselect commandsequence when the device is in the Erase Suspendmode. The device allows reading autoselect codeseven at addresses within erasing sectors, since thecodes are not stored in the memory array. When the

Am29LV160B21

device exits the autoselect mode, the device reverts tothe Erase Suspend mode, and is ready for anothervalid operation. See “Autoselect Command Sequence”for more information.

The system must write the Erase Resume command(address bits are “don’t care”) to exit the erase suspendmode and continue the sector erase operation. Furtherwrites of the Resume command are ignored. AnotherErase Suspend command can be written after the de-vice has resumed erasing.

STARTWrite Erase Command SequenceData Poll from SystemNoEmbedded Erasealgorithmin progressData = FFh?YesErasure Completed21358G-8Notes:1.See Table 9 for erase command sequence.2.See “DQ3: Sector Erase Timer” for more information.Figure 4.Erase Operation

22Am29LV160B

Table 9.

CommandSequence(Note 1)

Read (Note 6)Reset (Note 7)

Manufacturer ID

WordByteWordByteWordByteWord

4

Byte

143226611

AAA55AA555AAA555AAAXXXXXX555AAA555AAAXXXXXX

Am29LV160B Command Definitions

Bus Cycles (Notes 2–5)

Second Third Fourth Fifth Sixth AddrDataAddrDataAddrDataAddrDataAddrData

Cycles1

1444

Autoselect (Note 8)Device ID,

Top Boot Block Device ID,

Bottom Boot BlockSector Protect Verify (Note 9)

FirstAddrDataRARDXXXF0555

AA

AAA555

AA

AAA555

AA

AAA555

AA

2AA5552AA5552AA5552AA

555555

555AAA555AAA555AAA555

909090

X00X01

X02

0122C4C4224949XX00XX010001

X01

X02

55

555

AAA

90

(SA)X02(SA)X04

WordByteWord

Program

ByteWord

Unlock Bypass

Byte

Unlock Bypass Program (Note 11)Unlock Bypass Reset (Note 12)

Word

Chip Erase

ByteWord

Sector Erase

Byte

Erase Suspend (Note 13)Erase Resume (Note 14)CFI Query (Note 10)

98AAAAA090AAAAB030

2AA5552AA555PAXXX2AA5552AA555

5555PD005555

555AAA555AAA

8080

555AAA555AAA

AAAA

2AA5552AA555

5555

555AAASA

1030

555AAA555AAA

A020

PA

PD

Legend:X = Don’t careRA = Address of the memory location to be read. RD = Data read from location RA during read operation.PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.Notes:1.See Table 1 for description of bus operations.2.All values are in hexadecimal.3.Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.4.Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.5.Address bits A19–A11 are don’t cares for unlock and command cycles, unless SA or PA required.6.No unlock or command cycles required when reading array data.7.The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data).8.The fourth cycle of the autoselect command sequence is a read cycle.9.The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.10.Command is valid when device is ready to read array data or when device is in autoselect mode.11.The Unlock Bypass command is required prior to the Unlock Bypass Program command.12.The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.13.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.14.The Erase Resume command is valid only during the Erase Suspend mode.PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector.Am29LV160B23

WRITE OPERATION STATUS

The device provides several bits to determine thestatus of a write operation: DQ2, DQ3, DQ5, DQ6,DQ7, and RY/BY#. Table 10 and the following subsec-tions describe the functions of these bits. DQ7,RY/BY#, and DQ6 each offer a method for determiningwhether a program or erase operation is complete or inprogress. These three bits are discussed first.

Table 10 shows the outputs for Data# Polling on DQ7.Figure 5 shows the Data# Polling algorithm.

STARTDQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the hostsystem whether an Embedded Algorithm is in progressor completed, or whether the device is in Erase Sus-pend. Data# Polling is valid after the rising edge of thefinal WE# pulse in the program or erase commandsequence.

During the Embedded Program algorithm, the deviceoutputs on DQ7 the complement of the datum pro-grammed to DQ7. This DQ7 status also applies to pro-gramming during Erase Suspend. When theEmbedded Program algorithm is complete, the deviceoutputs the datum programmed to DQ7. The systemmust provide the program address to read valid statusinformation on DQ7. If a program address falls within aprotected sector, Data# Polling on DQ7 is active forapproximately 1 µs, then the device returns to readingarray data.

During the Embedded Erase algorithm, Data# Pollingproduces a “0” on DQ7. When the Embedded Erasealgorithm is complete, or if the device enters the EraseSuspend mode, Data# Polling produces a “1” on DQ7.This is analogous to the complement/true datum outputdescribed for the Embedded Program algorithm: theerase function changes all the bits in a sector to “1”;prior to this, the device outputs the “complement,” or“0.” The system must provide an address within any ofthe sectors selected for erasure to read valid statusinformation on DQ7.

After an erase command sequence is written, if allsectors selected for erasing are protected, Data#Polling on DQ7 is active for approximately 100 µs, thenthe device returns to reading array data. If not allselected sectors are protected, the Embedded Erasealgorithm erases the unprotected sectors, and ignoresthe selected sectors that are protected.

When the system detects DQ7 has changed from thecomplement to true data, it can read valid data at DQ7–DQ0 on the following read cycles. This is because DQ7may change asynchronously with DQ0–DQ6 whileOutput Enable (OE#) is asserted low. Figure 19, Data#Polling Timings (During Embedded Algorithms), in the“AC Characteristics” section illustrates this.

Read DQ7–DQ0Addr = VADQ7 = Data?YesNoNoDQ5 = 1?YesRead DQ7–DQ0Addr = VADQ7 = Data?YesNoFAILPASSNotes:1.VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address.2.DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.21358G-9

Figure 5.Data# Polling Algorithm

24Am29LV160B

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin thatindicates whether an Embedded Algorithm is inprogress or complete. The RY/BY# status is valid afterthe rising edge of the final WE# pulse in the commandsequence. Since RY/BY# is an open-drain output,several RY/BY# pins can be tied together in parallelwith a pull-up resistor to VCC. (The RY/BY# pin is notavailable on the 44-pin SO package.)

If the output is low (Busy), the device is actively erasingor programming. (This includes programming in theErase Suspend mode.) If the output is high (Ready),the device is ready to read array data (including duringthe Erase Suspend mode), or is in the standby mode.Table 10 shows the outputs for RY/BY#. Figures 13, 14,17 and 18 shows RY/BY# for read, reset, program, anderase operations, respectively.

Table 10 shows the outputs for Toggle Bit I on DQ6.Figure 6 shows the toggle bit algorithm in flowchartform, and the section “Reading Toggle Bits DQ6/DQ2”explains the algorithm. Figure 20 in the “AC Character-istics” section shows the toggle bit timing diagrams.Figure 21 shows the differences between DQ2 andDQ6 in graphical form. See also the subsection on“DQ2: Toggle Bit II”.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-cates whether a particular sector is actively erasing(that is, the Embedded Erase algorithm is in progress),or whether that sector is erase-suspended. Toggle BitII is valid after the rising edge of the final WE# pulse inthe command sequence.

DQ2 toggles when the system reads at addresseswithin those sectors that have been selected for era-sure. (The system may use either OE# or CE# tocontrol the read cycles.) But DQ2 cannot distinguishwhether the sector is actively erasing or is erase-sus-pended. DQ6, by comparison, indicates whether thedevice is actively erasing, or is in Erase Suspend, butcannot distinguish which sectors are selected for era-sure. Thus, both status bits are required for sector andmode information. Refer to Table 10 to compareoutputs for DQ2 and DQ6.

Figure 6 shows the toggle bit algorithm in flowchartform, and the section “Reading Toggle Bits DQ6/DQ2”explains the algorithm. See also the DQ6: Toggle Bit Isubsection. Figure 20 shows the toggle bit timing dia-gram. Figure 21 shows the differences between DQ2and DQ6 in graphical form.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an EmbeddedProgram or Erase algorithm is in progress or complete,or whether the device has entered the Erase Suspendmode. Toggle Bit I may be read at any address, and isvalid after the rising edge of the final WE# pulse in thecommand sequence (prior to the program or eraseoperation), and during the sector erase time-out.During an Embedded Program or Erase algorithmoperation, successive read cycles to any addresscause DQ6 to toggle. (The system may use either OE#or CE# to control the read cycles.) When the operationis complete, DQ6 stops toggling.

After an erase command sequence is written, if allsectors selected for erasing are protected, DQ6 togglesfor approximately 100 µs, then returns to reading arraydata. If not all selected sectors are protected, theEmbedded Erase algorithm erases the unprotectedsectors, and ignores the selected sectors that are pro-tected.

The system can use DQ6 and DQ2 together to deter-mine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is,the Embedded Erase algorithm is in progress), DQ6toggles. When the device enters the Erase Suspendmode, DQ6 stops toggling. However, the system mustalso use DQ2 to determine which sectors are erasingor erase-suspended. Alternatively, the system can useDQ7 (see the subsection on “DQ7: Data# Polling”).If a program address falls within a protected sector,DQ6 toggles for approximately 1 µs after the programcommand sequence is written, then returns to readingarray data.

DQ6 also toggles during the erase-suspend-programmode, and stops toggling once the EmbeddedProgram algorithm is complete.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. When-ever the system initially begins reading toggle bit sta-tus, it must read DQ7–DQ0 at least twice in a row todetermine whether a toggle bit is toggling. Typically,the system would note and store the value of the tog-gle bit after the first read. After the second read, thesystem would compare the new value of the toggle bitwith the first. If the toggle bit is not toggling, the devicehas completed the program or erase operation. Thesystem can read array data on DQ7–DQ0 on the fol-lowing read cycle.

However, if after the initial two read cycles, the systemdetermines that the toggle bit is still toggling, thesystem also should note whether the value of DQ5 ishigh (see the section on DQ5). If it is, the systemshould then determine again whether the toggle bit istoggling, since the toggle bit may have stopped tog-gling just as DQ5 went high. If the toggle bit is no longertoggling, the device has successfully completed theprogram or erase operation. If it is still toggling, thedevice did not complete the operation successfully, and

Am29LV160B25

the system must write the reset command to return toreading array data.

The remaining scenario is that the system initiallydetermines that the toggle bit is toggling and DQ5 hasnot gone high. The system may continue to monitor thetoggle bit and DQ5 through successive read cycles,determining the status as described in the previousparagraph. Alternatively, it may choose to performother system tasks. In this case, the system must startat the beginning of the algorithm when it returns todetermine the status of the operation (top of Figure 6).

STARTRead DQ7–DQ0Read DQ7–DQ0(Note 1)Toggle Bit = Toggle?YesNoNoDQ5 = 1?YesRead DQ7–DQ0Twice(Notes 1, 2)Toggle Bit = Toggle?YesProgram/EraseOperation Not Complete, Write Reset CommandNoProgram/EraseOperation CompleteNotes: 1.Read toggle bit twice to determine whether or not it is toggling. See text.2.Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text.21358G-10

Figure 6.Toggle Bit Algorithm

26Am29LV160B

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time hasexceeded a specified internal pulse count limit. Underthese conditions DQ5 produces a “1.” This is a failurecondition that indicates the program or erase cycle wasnot successfully completed.

The DQ5 failure condition may appear if the systemtries to program a “1” to a location that is previously pro-grammed to “0.” Only an erase operation can changea “0” back to a “1.” Under this condition, the devicehalts the operation, and when the operation hasexceeded the timing limits, DQ5 produces a “1.”Under both these conditions, the system must issue thereset command to return the device to reading arraydata.

sectors are selected for erasure, the entire time-out alsoapplies after each additional sector erase command.When the time-out is complete, DQ3 switches from “0” to“1.” The system may ignore DQ3 if the system canguarantee that the time between additional sectorerase commands will always be less than 50 µs. Seealso the “Sector Erase Command Sequence” section.After the sector erase command sequence is written,the system should read the status on DQ7 (Data# Poll-ing) or DQ6 (Toggle Bit I) to ensure the device has ac-cepted the command sequence, and then read DQ3. IfDQ3 is “1”, the internally controlled erase cycle has be-gun; all further commands (other than Erase Suspend)are ignored until the erase operation is complete. IfDQ3 is “0”, the device will accept additional sectorerase commands. To ensure the command has beenaccepted, the system software should check the statusof DQ3 prior to and following each subsequent sectorerase command. If DQ3 is high on the second statuscheck, the last command might not have been ac-cepted. Table 10 shows the outputs for DQ3.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, thesystem may read DQ3 to determine whether or not anerase operation has begun. (The sector erase timerdoes not apply to the chip erase command.) If additional

Table 10.

Operation

Standard Embedded Program AlgorithmModeEmbedded Erase AlgorithmErase Suspend Mode

Reading within Erase Suspended SectorReading within Non-Erase Suspended SectorErase-Suspend-Program

Write Operation Status

DQ6ToggleToggleNo toggleDataToggle

DQ5(Note 1)

000Data0

DQ3N/A1N/ADataN/A

DQ2(Note 2)No toggleToggleToggleDataN/A

RY/BY#

00110

DQ7(Note 2)DQ7#01DataDQ7#

Notes:1.DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5: Exceeded Timing Limits” for more information.2.DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.Am29LV160B27

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°CAmbient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°CVoltage with Respect to Ground

VCC (Note 1). . . . . . . . . . . . . . . . . .–0.5 V to +4.0 VA9, OE#, and RESET# (Note 2). .–0.5 V to +12.5 VAll other pins (Note 1). . . . . . . –0.5 V to VCC+0.5 VOutput Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:1.Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7 . Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8 .2.Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7 . Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.3.No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°CIndustrial (I) Devices

Ambient Temperature (TA) . . . . . . . . .–40°C to +85°CExtended (E) Devices

Ambient Temperature (TA) . . . . . . . .–55°C to +125°CVCC Supply Voltages

VCC for regulated voltage range . . . . . . 3.0 V to 3.6 VVCC for full voltage range . . . . . . . . . . . 2.7 V to 3.6 V

Operating ranges define those limits between which the func-tionality of the device is guaranteed.20 ns+0.8 V–0.5 V–2.0 V20 ns20 nsVCC+2.0 VVCC+0.5 V2.0 V

20 ns20 ns20 ns21358G-12

21358G-11

Figure 7.

Maximum Negative Overshoot

Waveform

Figure 8.

Maximum Positive Overshoot

Waveform

28Am29LV160B

DC CHARACTERISTICSCMOS Compatible

Parameter

ILIILITILO

Description

Input Load CurrentA9 Input Load CurrentOutput Leakage Current

Test Conditions

VIN = VSS to VCC, VCC = VCC max

VCC = VCC max; A9 = 12.5 VVOUT = VSS to VCC, VCC = VCC maxCE# = VIL, OE# = VIH,Byte Mode

CE# = VIL, OE# = VIH,Word Mode

CE# = VIL, OE# = VIHCE#, RESET# = VCC±0.3 V

5 MHz1 MHz5 MHz1 MHz

9292200.20.20.2

–0.50.7 x VCC

VCC = 3.3 V

11.5Min

Typ

Max±1.035±1.011305550.8VCC + 0.312.5

mAµAµAµAVVVVVmAUnitµAµAµA

ICC1

VCC Active Read Current (Notes 1, 2)

ICC2ICC3ICC4ICC5VILVIHVIDVOLVOH1VOH2VLKO

VCC Active Write Current (Notes 2, 3, 4)

VCC Standby Current (Note 2)

VCC Standby Current During Reset

RESET# = VSS ± 0.3 V

(Note 2)

Automatic Sleep Mode (Notes 2, 5)Input Low VoltageInput High Voltage

Voltage for Autoselect and Temporary Sector UnprotectOutput Low VoltageOutput High Voltage

Low VCC Lock-Out Voltage (Note 4)

VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V

IOL = 4.0 mA, VCC = VCC min 0.45IOH = -2.0 mA, VCC = VCC min IOH = -100 µA, VCC = VCC min

0.85 x VCCVCC–0.42.3

2.5

V

Notes:1.The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.2.Maximum ICC specifications are tested with VCC = VCCmax.3.ICC active while Embedded Erase or Embedded Program is in progress.4.Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA.5.Not 100% tested.Am29LV160B29

DC CHARACTERISTICS (Continued)Zero Power Flash

25Supply Current in mA20151050

0

500

1000

1500

2000Time in ns

Note:Addresses are switching at 1 MHz21358G-13

2500300035004000

Figure 9.

ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

10

3.6 V

8Supply Current in mA2.7 V

6

4

2

01

2

3

Frequency in MHz

Note:T = 25 °C21358G-14

45

Figure 10.

Typical ICC1 vs. Frequency

30Am29LV160B

TEST CONDITIONS

3.3 V

2.7 kΩ

Table 11.

Test Condition

Test Specifications

70R,80

90,1201 TTL gate 30

50.0–3.0

100

pFnsVUnit

DeviceUnderTest

CL

6.2 kΩ

Output Load

Output Load Capacitance, CL(including jig capacitance) Input Rise and Fall TimesInput Pulse LevelsInput timing measurement reference levels

1.5 V1.5

V

Note: Diodes are IN30 or equivalent21358G-15

Output timing measurement reference levels

Figure 11.Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

Steady

Changing from H to LChanging from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

OUTPUTS

KS000010-PAL

3.0 V0.0 VInput1.5 VMeasurement Level1.5 VOutput21358G-16

Figure 12.Input Waveforms and Measurement Levels

Am29LV160B31

AC CHARACTERISTICSRead Operations

ParameterJEDECtAVAVtAVQVtELQVtGLQVtEHQZtGHQZ

StdtRCtACCtCEtOEtDFtDFtOEH

Description

Read Cycle Time (Note 1)Address to Output DelayChip Enable to Output DelayOutput Enable to Output DelayChip Enable to Output High Z (Note 1)Output Enable to Output High Z (Note 1)Read

Output Enable

Hold Time (Note 1)Toggle and

Data# PollingOutput Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1)

CE# = VILOE# = VILOE# = VIL

Test Setup

MinMaxMaxMaxMaxMaxMinMinMin

70R707070302525

Speed Options80808080302525

0100

90909090353030

120120120120503030

Unitnsnsnsnsnsnsnsnsns

tAXQXtOH

Notes:1.Not 100% tested.2.See Figure 11 and Table 11 for test specifications.tRCAddressesCE#tOEtOEHWE#HIGH ZtCEOutput ValidtOHHIGH ZtDFAddresses StabletACCOE#OutputsRESET#RY/BY#0 V21358G-17

Figure 13.Read Operations Timings

32Am29LV160B

AC CHARACTERISTICSHardware Reset (RESET#)

ParameterJEDEC

StdtREADYtREADYtRPtRHtRPDtRB

Description

RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note)

RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note)RESET# Pulse Width

RESET# High Time Before Read (See Note)RESET# Low to Standby ModeRY/BY# Recovery Time

Test Setup

MaxMaxMinMinMinMin

All Speed Options

2050050050200

Unitµsnsnsnsµsns

Note:Not 100% tested.RY/BY#CE#, OE#tRHRESET#tRPtReadyReset Timings NOT during Embedded AlgorithmsReset Timings during Embedded AlgorithmstReadyRY/BY#tRBCE#, OE#RESET#tRP21358G-18

Figure 14.RESET# Timings

Am29LV160B33

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

JEDEC

StdtELFL/tELFHtFLQZtFHQV

CE#Description

CE# to BYTE# Switching Low or HighBYTE# Switching Low to Output HIGH ZBYTE# Switching High to Output Active

MaxMax Min

2570

2580

70R

Speed Options80

5

3090

30120

90

120

Unitnsnsns

OE#

BYTE#

tELFLBYTE#Switchingfrom wordto bytemode

DQ0–DQ14

Data Output(DQ0–DQ14)DQ15OutputtFLQZData Output(DQ0–DQ7)AddressInputDQ15/A-1

tELFHBYTE#

BYTE#Switchingfrom byteto wordmode

DQ0–DQ14

Data Output(DQ0–DQ7)AddressInputtFHQVData Output(DQ0–DQ14)DQ15OutputDQ15/A-1

21358G-19

Figure 15.BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signalWE#

BYTE#

tSET(tAS)tHOLD (tAH)

Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.21358G-20

Figure 16.BYTE# Timings for Write Operations

34Am29LV160B

AC CHARACTERISTICSErase/Program Operations

ParameterJEDECtAVAVtAVWLtWLAXtDVWHtWHDX

StdtWCtAStAHtDStDHtOES

tGHWLtELWLtWHEHtWLWHtWHWLtWHWH1tWHWH2

tGHWLtCStCHtWPtWPHtWHWH1tWHWH2tVCStRBtBUSY

Description

Write Cycle Time (Note 1)Address Setup TimeAddress Hold TimeData Setup TimeData Hold Time

Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low)CE# Setup TimeCE# Hold TimeWrite Pulse WidthWrite Pulse Width High

Programming Operation (Note 2)Sector Erase Operation (Note 2)VCC Setup Time (Note 1)Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

ByteWord

MinMinMinMinMinMinMinMinMinMinMinTypTypTypMinMinMin

35

35

309110.750090

4535

4535

00000

35

50

70R70

Speed Options8080

0

4545

5050

9090

120120

Unitnsnsnsnsnsnsnsnsnsnsnsµssecµsnsns

Notes:1.Not 100% tested.2.See the “Erase and Programming Performance” section for more information.Am29LV160B35

AC CHARACTERISTICS

Program Command Sequence (last two cycles)tAStWCAddresses555hPAtAHCE#tGHWLOE#tWPWE#tCStDSDatatDHPDtBUSYRY/BY#tVCSVCC21358G-21Read Status Data (last two cycles)PAPAtCHtWHWH1tWPHA0hStatusDOUTtRBNotes:1.PA = program address, PD = program data, DOUT is the true data at the program address.2.Illustration shows device in word mode.Figure 17.Program Operation Timings

36Am29LV160B

AC CHARACTERISTICS Erase Command Sequence (last two cycles)tWCAddresses2AAhtASSA555h for chip eraseRead Status DataVAtAHVACE#tGHWLOE#tWPWE#tCStDStDHData55h30h10 for Chip EraseInProgressCompletetCHtWPHtWHWH2tBUSYRY/BY#tVCSVCCtRB21358G-22Notes:1.SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).2.Illustration shows device in word mode.Figure 18.Chip/Sector Erase Operation Timings

Am29LV160B37

AC CHARACTERISTICS

tRCAddressesVAtACCCE#tCHOE#tOEHWE#tOHDQ7ComplementComplementTrueValid DataHigh ZVAVAtCEtOEtDFDQ0–DQ6tBUSYRY/BY#Status DataStatus DataTrueValid DataHigh ZNote:VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.21358G-23

Figure 19.Data# Polling Timings (During Embedded Algorithms)

tRCAddressesVAtACCCE#tCHOE#tOEHWE#tOHDQ6/DQ2tBUSYRY/BY#High ZVAVAVAtCEtOEtDFValid Status(first read)Valid Status(second read)Valid Status(stops toggling)Valid DataNote:VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.21358G-24

Figure 20.Toggle Bit Timings (During Embedded Algorithms)

38Am29LV160B

AC CHARACTERISTICS

EnterEmbeddedErasing

WE#

EraseSuspendEraseEnter EraseSuspend Program

EraseSuspendProgram

EraseResume

Erase Suspend

Read

Erase

EraseComplete

Erase SuspendRead

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. 21358G-25

Figure 21.DQ2 vs. DQ6 for Erase and Erase Suspend Operations

Temporary Sector Unprotect

ParameterJEDEC

StdtVIDRtRSP

Description

VID Rise and Fall Time (See Note)RESET# Setup Time for Temporary Sector Unprotect

MinMin

All Speed Options

5004

Unitnsµs

Note:Not 100% tested. 12 VRESET#0 or 3 VtVIDRProgram or Erase Command SequencetVIDRCE#WE#tRSPRY/BY# 21358G-26

Figure 22.Temporary Sector Unprotect Timing Diagram

Am29LV160B39

AC CHARACTERISTICS

VIDVIHRESET#SA, A6,A1, A0Valid*Sector Protect/UnprotectValid*Verify40hSector Protect: 150 µsSector Unprotect: 15 msValid*Data1 µsCE#60h60hStatusWE#OE#Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.21358G-27

Figure 23.Sector Protect/Unprotect Timing Diagram

40Am29LV160B

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

ParameterJEDECtAVAVtAVELtELAXtDVEHtEHDX

StdtWCtAStAHtDStDHtOES

tGHELtWLELtEHWHtELEHtEHELtWHWH1tWHWH2

tGHELtWStWHtCPtCPHtWHWH1tWHWH2

Description

Write Cycle Time (Note 1)Address Setup TimeAddress Hold TimeData Setup TimeData Hold Time

Output Enable Setup TimeRead Recovery Time Before Write (OE# High to WE# Low)WE# Setup TimeWE# Hold TimeCE# Pulse WidthCE# Pulse Width High

Programming Operation (Note 2)Sector Erase Operation (Note 2)

ByteWord

MinMinMinMinMinMinMinMinMinMinMinTypTypTyp

35

35

309110.7

4535

4535

00000

35

50

70R70

Speed Options8080

0

4545

5050

9090

120120

Unitnsnsnsnsnsnsnsnsnsnsnsµssec

Notes:1.Not 100% tested.2.See the “Erase and Programming Performance” section for more information.Am29LV160B41

AC CHARACTERISTICS

555 for program2AA for erase PA for programSA for sector erase555 for chip erase Data# PollingPAAddressestWCtWHWE#tGHELOE#tCPCE#tWStCPHtDStDHDatatRHA0 for program55 for erase PD for program30 for sector erase10 for chip erase tAStAHtWHWH1 or 2tBUSYDQ7#DOUTRESET#RY/BY#Notes: 1.PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2.Figure indicates the last two bus cycles of the command sequence.3.Word mode address used as an example.21358G-28

Figure 24.Alternate CE# Controlled Write Operation Timings

42Am29LV160B

ERASE AND PROGRAMMING PERFORMANCE

ParameterSector Erase TimeChip Erase Time Byte Programming TimeWord Programming TimeChip Programming Time(Note 3)

Byte ModeWord Mode

Typ (Note 1)

0.7259111812

300360 5436Max (Note 2)

15

Unitssµsµsss

Excludes system level overhead (Note 5)

Comments

Excludes 00h programming prior to erasure (Note 4)

Notes:1.Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern.2.Under worst case conditions of 90°C, VCC = 2.7 V (3.0 V for 70R), 1,000,000 cycles.3.The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed.4.In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.5.System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 9 for further information on command definitions.6.The device has a minimum erase and program cycle endurance of 1,000,000 cycles.LATCHUP CHARACTERISTICS

Description

Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#)

Input voltage with respect to VSS on all I/O pinsVCC Current

Min–1.0 V–1.0 V–100 mA

Max12.5 VVCC + 1.0 V+100 mA

Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.TSOP AND SO PIN CAPACITANCE

Parameter Symbol

CINCOUTCIN2

Parameter DescriptionInput CapacitanceOutput CapacitanceControl Pin Capacitance

Test SetupVIN = 0VOUT = 0VIN = 0

Typ68.57.5

Max7.5129

UnitpFpFpF

Notes:1.Sampled, not 100% tested.2.Test conditions TA = 25°C, f = 1.0 MHz.DATA RETENTION

Parameter

Minimum Pattern Data Retention Time

Test Conditions

150°C125°C

Min1020

UnitYearsYears

Am29LV160B43

PHYSICAL DIMENSIONS*

TS 048—48-Pin Standard TSOP (measured in millimeters)

0.951.05Pin 1 I.D.14811.9012.100.50 BSC242518.3018.5019.8020.200.080.200.100.210.050.151.20MAX0.25MM (0.0098\") BSC0˚5˚0.500.7016-038-TS48-2TS 048DT958-8-96 lv* For reference only. BSC is an ANSI standard for Basic Space Centering.TSR048—48-Pin Reverse TSOP (measured in millimeters)

0.951.05Pin 1 I.D.14811.9012.100.50 BSC242518.3018.5019.8020.20SEATING PLANE0.050.151.20MAX0.25MM (0.0098\") BSC0˚5˚0.500.700.080.200.100.2116-038-TS48TSR048DT958-8-96 lv* For reference only. BSC is an ANSI standard for Basic Space Centering.44Am29LV160B

PHYSICAL DIMENSIONS

FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 8 x 9 mm (measured in millimeters)

0.20(4X)9.00 BSCA8.00 BSCB1.001.200.840.940.25Z0.200.305.60 BSCZ0.10Z0.40BSC.4.00 BSC0.80BSC0.250.350.40 BSC.PIN 1 ID16-038-FBA-2_AAET15311.6.98 lv.25MZAB.10MZAm29LV160B45

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package (measured in millimeters)

442313.1013.5015.7016.3011.27 NOM.TOP VIEW2228.0028.402.172.450.350.50SIDE VIEW0.100.350.100.21SEATINGPLANE0˚8˚END VIEW16-038-SO44-2SO 044DF838-8-96 lv2.80MAX.0.601.0046Am29LV160B

REVISION SUMMARYRevision F

Distinctive Characteristics

Changed typical read and program/erase currentspecifications.

Device now has a guaranteed minimum endurance of1,000,000 write cycles.

Figure 2, In-System Sector Protect/Unprotect Algorithms (0.35 µm devices)

Corrected A6 to 0, Changed wait specification to 150 µson sector protect and 15 ms on sector unprotect.DC Characteristics

Changed typical read and program/erase currentspecifications.AC Characteristics

100% tested. Corrected the note reference for tVCS.This parameter is not 100% tested.Temporary Sector Unprotect Table

Added note reference for tVIDR. This parameter is not100% tested.

Figure 23, Sector Protect/Unprotect Timing Diagram

A valid address is not required for the first write cycle;only the data 60h.

Erase and Programming Performance

In Note 2, the worst case endurance is now 1 million cycles.

Revision G

Global

Added 70R speed option, changed 80R speed optionto 80.

Distinctive Characteristics

Changed process technology to 0.32 µm.DC Characteristics

Moved VCCmax test condition for ICC specificationstonotes.

Connection Diagrams

Corrected the reverse TSOP drawing to show orienta-tion and pin 1 indicators.Distinctive CharacteristicsAdded 20-year data retention bullet.Connection DiagramsUpdated FBGA figure.Ordering Information

Changed FBGA package reference to FBC048;addded FBGA package marking information.Physical DimensionsChanged drawing to FBC048.

Alternate CE# Controlled Erase/Program Operations:Changed tCP to 35 ns for 70R, 80, and 90 speedoptions.2w

Erase and Programming Performance

Device now has a guaranteed minimum endurance of1,000,000 write cycles.Physical Dimensions

Corrected dimensions for package length and width inFBGA illustration (standalone data sheet version).

Revision F+1

Table 9, Command Definitions

Corrected the byte-mode address in the sixth writecycle of the chip erase command sequence to AAAh.

Revision F+2

Figure 2, In-System Sector Protect/Unprotect Algorithms (0.35 µm devices)

In the sector protect algorithm, added a “ResetPLSCNT=1” box in the path from “Protect another sec-tor?” back to setting up the next sector address.DC Characteristics

Changed ICC1 test conditions and Note 1 to indicatethat OE# is at VIH for the listed current.AC Characteristics

Revision G+1

Connection Diagrams

Erase/Program Operations; Alternate CE# ControlledErase/Program Operations: Corrected the notes refer-ence for tWHWH1 and tWHWH2. These parameters are

FBGA: Corrected to indicate that diagram shows thetop view, balls facing down.Command Definitions Table

Corrected the address in the sixth cycle of the chiperase sequence to AAAh.

TrademarksCopyright © 1999 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for iden-tification purposes only and may be trademarks of their respective companies.

Am29LV160B47