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专利名称：Tool and method for improving the quality
of board design and modeling
发明人：Nick Andrew Van Stralen申请号：US09803431申请日：20010309
公开号：US20020004931A1公开日：20020110
专利附图：
摘要：The present invention provides a design tool and method which creates a VHSICHardware Description Language (VHDL) board model that can be used by digitalengineers to verify their ASIC and FPGA designs. (VHSIC is an acronym for Very High
Speed Integrated Circuits.) The board model is used as part of the test bench that teststhe functionality of the board. Any models of the component parts can be instantiated inthe board model using a “configuration” statement in the VHDL. Any inconsistenciesbetween the board requirements and the ASIC and FPGA specifications can be identified.
申请人：STRALEN NICK ANDREW VAN
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